{"id":599891,"date":"2021-01-06T15:15:25","date_gmt":"2021-01-06T14:15:25","guid":{"rendered":"https:\/\/www.tomshardware.fr\/?p=599891"},"modified":"2023-06-22T17:21:01","modified_gmt":"2023-06-22T15:21:01","slug":"amd-voudrait-integrer-des-fpga-dans-ses-cpu","status":"publish","type":"post","link":"https:\/\/www.tomshardware.fr\/amd-voudrait-integrer-des-fpga-dans-ses-cpu\/","title":{"rendered":"AMD voudrait int\u00e9grer des FPGA dans ses CPU"},"content":{"rendered":"\n

Apr\u00e8s l’abandon d’une architecture monolithique au profit d’une conception \u00e0 base chiplets dans ses processeurs depuis l\u2019architecture Zen 2, AMD pourrait apporter une nouvelle \u00e9volution avec l’int\u00e9gration de FPGA (Field Programmable Gate Arrays<\/em>) dans ses CPU ; un autre moyen d’augmenter les performances de ses puces.<\/p>\n\n\n\n

\"Image<\/a><\/figure><\/div>\n\n\n\n

La soci\u00e9t\u00e9 a d\u00e9pos\u00e9 un brevet<\/a> intitul\u00e9 “METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE INSTRUCTIONS IN COMPUTER SYSTEMS”<\/em>. Si beaucoup de brevets ne trouvent jamais d\u2019applications concr\u00e8tes, celui-ci est quand m\u00eame soutenu par le rachat de Xilinx<\/a>, \u00e0 l’origine du FPGA, par AMD en octobre dernier. On suppose que la soci\u00e9t\u00e9 dirig\u00e9e par Lisa Su n\u2019a pas d\u00e9bours\u00e9 35 milliards de dollars sans avoir quelques projets\u2026<\/p>\n\n\n\n

AMD planche sur des GPU \u00e0 base de chiplets<\/a><\/strong><\/p>\n\n\n\n

Un moyen d\u2019augmenter les performances<\/h2>\n\n\n\n

L\u2019int\u00e9gration de FPGA au sein de CPU pourraient se traduire par une hausse des performances non n\u00e9gligeable. Un processeur x86 classique est con\u00e7u pour ex\u00e9cuter un large panel d\u2019instructions, avec plus ou moins d\u2019habilit\u00e9 ; tout le contraire d\u2019un FPGA, tr\u00e8s sp\u00e9cialis\u00e9, capable d\u2019ex\u00e9cuter rapidement des jeux d\u2019instructions sp\u00e9cifiques. En outre, comme leur nom l’indique, ils ont l\u2019avantage d\u2019\u00eatre reprogrammables facilement, autrement dit de s\u2019adapter \u00e0 d\u2019autres t\u00e2ches au besoin. Sch\u00e9matiquement, l\u2019id\u00e9e derri\u00e8re ce brevet consisterait \u00e0 confier certains calculs sp\u00e9cifiques au module FPGA afin qu\u2019il les traite plus rapidement que ne le feraient les c\u0153urs CPU.<\/p>\n\n\n\n

Comme le rapporte TechPowerUp<\/a>, une telle association existe d\u00e9j\u00e0 chez Intel, avec le Xeon 6138P. Ce processeur associe CPU et FPGA Arria 10 GX 1150. N\u00e9anmoins, les deux \u00e9l\u00e9ments prennent place sur le m\u00eame die, mais ne sont pas vraiment int\u00e9gr\u00e9s nativement ; le Xeon 6138P est “simplement” une puce 2-en-1 en quelque sorte.<\/p>\n\n\n\n

\n
\n
\"Image<\/a><\/figure><\/div>\n<\/div>\n\n\n\n
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\"Image<\/a><\/figure><\/div>\n<\/div>\n<\/div>\n\n\n\n

AMD pourrait pousser le concept \u00e0 stade plus avanc\u00e9, avec une int\u00e9gration compl\u00e8te CPU \/ FPGA. Pour cela, la firme a deux options. Pour rester dans la philosophie des chiplets, le FPGA pourrait r\u00e9sider dans son propre chiplet, \u00e0 l\u2019\u00e9cart. Dans ce cas, il serait interconnect\u00e9 avec le CPU par l\u2019Infinity Fabric. Cette m\u00e9thode pr\u00e9sente l\u2019avantage de ne pas trop chambouler l\u2019architecture des processeurs, mais peut induire de la latence. L\u2019autre solution, plus radicale, consisterait \u00e0 int\u00e9grer le FPGA directement au sein des chiplets contenant les c\u0153urs CPU. Cette strat\u00e9gie minimiserait la latence, mais impliquerait de r\u00e9organiser en profondeur les CCD (Core Complex Die<\/em>).<\/p>\n\n\n\n

Sources : Tom’s Hardware US<\/a>, WikiChip<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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