{"id":794384,"date":"2023-05-10T17:45:00","date_gmt":"2023-05-10T15:45:00","guid":{"rendered":"https:\/\/www.tomshardware.fr\/?p=794384"},"modified":"2023-06-22T16:39:46","modified_gmt":"2023-06-22T14:39:46","slug":"le-processeur-europeen-occamy-qui-sera-utilise-par-lesa-est-finalise","status":"publish","type":"post","link":"https:\/\/www.tomshardware.fr\/le-processeur-europeen-occamy-qui-sera-utilise-par-lesa-est-finalise\/","title":{"rendered":"Le processeur europ\u00e9en Occamy, qui sera utilis\u00e9 par l’ESA, est finalis\u00e9"},"content":{"rendered":"\n

Le processeur Occamy, d\u00e9velopp\u00e9e par des ing\u00e9nieurs de l’ETH Z\u00fcrich et de l’Universit\u00e9 de Bologne pour le compte de l\u2019ESA (Agence spatiale europ\u00e9enne) a atteint la phase du tape-out, autrement dit a achev\u00e9 son processus de conception. C\u2019est une processeur \u00e0 base chiplets dot\u00e9 de 432 c\u0153urs RISC-V et de 32 Go de m\u00e9moire HBM2E.<\/p>\n\n\n

\n
\"Image<\/a>
\u00a9 HPC Wire<\/figcaption><\/figure><\/div>\n\n\n

Plus pr\u00e9cis\u00e9ment, l\u2019Occamy consiste en deux chiplets de 216 c\u0153urs RISC-V 32 bits, auxquels s\u2019ajoutent une quantit\u00e9 non sp\u00e9cifi\u00e9e de FPU (floating-point unit<\/em>) 64 bits et deux puces m\u00e9moire HBM2E de 16 Go de Micron. Les c\u0153urs sont interconnect\u00e9s \u00e0 l’aide d’un interposeur en silicium. Les performances FP64 s\u2019\u00e9l\u00e8vent \u00e0 0,75 TFLOPS, les performances FP8 \u00e0 6 TFLOPS. La consommation n\u2019est pas renseign\u00e9e, mais le processeur est pr\u00e9sent\u00e9 comme une puce \u00e0 faible consommation d’\u00e9nergie qui peut-\u00eatre refroidie passivement. Enfin, la fabrication de ce processeur est confi\u00e9e \u00e0 GlobalFoundries sur son processus de fabrication 14LPP (14 nm). La mise en \u0153uvre a \u00e9t\u00e9 test\u00e9e sur les FPGA AMD Xilinx Virtex UltraScale+ HBM et sur le FPGA Virtex UltraScale+ VCU1525.<\/p>\n\n\n\n

\u00c0 lire > L\u2019Europe veut des centres de donn\u00e9es dans l\u2019espace<\/a><\/strong><\/p>\n\n\n\n

Un processeur parmi d’autres<\/h2>\n\n\n\n

Le communiqu\u00e9 stipule que \u00ab la puce \u00e0 432 c\u0153urs est une combinaison int\u00e9ressante d’anciennes et de nouvelles technologies, et a \u00e9t\u00e9 con\u00e7ue selon l’approche relativement nouvelle du chiplet. La conception des chiplets permet de m\u00e9langer et d’assortir des technologies anciennes et nouvelles – telles que des processeurs analogiques ou num\u00e9riques – \u00e0 l’int\u00e9rieur d’un bo\u00eetier de puce. \u00bb<\/p>\n\n\n\n

Il est \u00e9galement \u00e9crit que \u00ab Occamy est une puce \u00e0 faible consommation d’\u00e9nergie pour l’IA et les charges de travail informatiques \u00e0 haute performance. Les charges de travail d’IA reposent aujourd’hui en grande partie sur des acc\u00e9l\u00e9rateurs tels que les GPU et les c\u0153urs d’IA pour l’entra\u00eenement et l’inf\u00e9rence, et les chercheurs esp\u00e8rent que la puce open-source pourra \u00e9galement \u00eatre utilis\u00e9e dans les charges de travail d’IA terrestres. \u00bb<\/p>\n\n\n\n

Plus g\u00e9n\u00e9ralement, ce CPU Occamy est d\u00e9velopp\u00e9 dans le cadre du programme EuPilot, lequel ambitionne de \u00ab mettre au point des processeurs nationaux afin de r\u00e9duire la d\u00e9pendance \u00e0 l’\u00e9gard des puces x86 et ARM propri\u00e9taires. \u00bb<\/p>\n\n\n\n

\u00c0 lire > Les processeurs dans l\u2019espace, de 1965 \u00e0 nos jours<\/a><\/strong><\/p>\n\n\n\n

Pour finir, sachez que l\u2019EPI (European Processor Initiative<\/em>) vise au d\u00e9veloppement de processeurs pour les supercalculateurs, l’IA, l’IdO et les voitures autonomes. Ce projet englobe aussi le microprocesseur HPC europ\u00e9en d\u00e9velopp\u00e9 par SiPearl<\/a>, entre autres.<\/p>\n\n\n\n

Source : HPC Wire<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

Une puce RISC-V, \u00e0 base de chiplets, disposant de 432 c\u0153urs et de m\u00e9moire HBM2e. Elle d\u00e9livre des performances FP64 et FP8 de respectivement 0,75 TFLOPS et 6 TFLOPS. Ce processeur s'inscrit dans le cadre\u2026<\/p>","protected":false},"author":87,"featured_media":794385,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[487,4071],"tags":[],"hubs":[],"class_list":["post-794384","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-actualite","category-processeurs"],"acf":{"display_mode":"medium-img","post_show_excerpt":true,"post_show_in_home":true,"post_show_summary":false,"post_source":"","hide_sidebar":false,"hide_advertising":false},"yoast_head":"\nLe processeur europ\u00e9en Occamy, qui sera utilis\u00e9 par l'ESA, est finalis\u00e9<\/title>\n<meta name=\"description\" content=\"Une puce RISC-V, \u00e0 base de chiplets, disposant de 432 c\u0153urs et de m\u00e9moire HBM2e. Elle d\u00e9livre des performances FP64 et FP8 de respectivement 0,75 TFLOPS et 6 TFLOPS. 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